Atomic Effective Pseudopotentials for Semiconductors

We derive an analytic connection between the screened self-consistent effective potential from density functional theory (DFT) and atomic effective pseudopotentials (AEPs). The motivation to derive AEPs is to address structures with thousands to hundred thousand atoms, as given in most nanostructures. The use of AEPs allows to bypass a self-consistent procedure and to address eigenstates around a certain region of the spectrum (e.g., around the band gap). The bulk AEP construction requires two simple DFT calculations of slightly deformed elongated cells. The ensuing AEPs are given on a fine reciprocal space grid, including the small reciprocal vector components, are free of parameters, and involve no fitting procedure. We further show how to connect the AEPs of different bulk materials, which is necessary to obtain accurate band offsets. We derive a total of 20 AEPs for III-V, II-VI and group IV semiconductors and demonstrate their accuracy and transferability by comparison to DFT calculations of strained bulk structures, quantum wells with varying thickness, and semiconductor alloys.Comment: 10 pages, 5 figures, submitted to PR

Limitations to Electrical Probing of Spontaneous Polarization in Ferroelectric-Dielectric Heterostructures

An accurate estimate of the ferroelectric polarization in ferroelectric-dielectric stacks is important from a materials science perspective, and it is also crucial for the development of ferroelectric based electron devices. This paper revisits the theory and application of the PUND technique in Metal-Ferroelectric-Dielectric-Metal (MFDM) structures by using analytical derivations and numerical simulations. In an MFDM structure the results of the PUND technique may largely differ from the polarization actually switched in the stack, which in turn is different from the remnant polarization of the underlying ferroelectric. The main hindrances that prevent PUND measurements from providing a good estimate of the polarization switching in MFDM stacks are thus discussed. The inspection of the involved physical quantities, not always accessible in experiments, provides a useful insight about the main sources of the errors in the PUND technique, and clarifies the delicate interplay between the depolarization field and the charge injection and trapping in MFDM stacks with a thin dielectric layer

Ohmic Behavior in Metal Contacts to n/p-Type Transition-Metal Dichalcogenides: Schottky versus Tunneling Barrier Trade-off

High contact resistance (RC) between 3D metallic conductors and single-layer 2D semiconductors poses major challenges toward their integration in nanoscale electronic devices. While in experiments the large RC values can be partly due to defects, ab initio simulations suggest that, even in defect-free structures, the interaction between metal and semiconductor orbitals can induce gap states that pin the Fermi level in the semiconductor band gap, increase the Schottky barrier height (SBH), and thus degrade the contact resistance. In this paper, we investigate, by using an in-house-developed ab initio transport methodology that combines density functional theory and nonequilibrium Green’s function (NEGF) transport calculations, the physical properties and electrical resistance of several options for n-type top metal contacts to monolayer MoS2, even in the presence of buffer layers, and for p-type contacts to monolayer WSe2. The delicate interplay between the SBH and tunneling barrier thickness is quantitatively analyzed, confirming the excellent properties of the Bi-MoS2 system as an n-type ohmic contact. Moreover, simulation results supported by literature experiments suggest that the Au-WSe2 system is a promising candidate for p-type ohmic contacts. Finally, our analysis also reveals that a small modulation of a few angstroms of the distance between the (semi)metal and the transition-metal dichalcogenide (TMD) leads to large variations of RC. This could help to explain the scattering of RC values experimentally reported in the literature because different metal deposition techniques can result in small changes of the metal-to-TMD distance besides affecting the density of possible defects

Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs

NTRODUCTION \u2015 In the past decade the Tunnel Field Effect Transistor (TFET) relying on band-to-band tunneling (BTBT) has emerged as one of the most promising small slope FETs able to achieve a subthreshold swing (SS) below the room temperature 60 mV/dec limit of conventional MOSFET [1]. Many simulation studies attributed to TFETs the potential to outperform conventional MOSFETs in the ultra-low voltage domain (VDD < 0.4 V) in both analog [2-3] and digital [4-7] applications. However, only basic digital and analog circuits have been fabricated up to date, such as current mirrors [8] and inverter gates [9]. As for semiconductor materials, III-V hetero-structure TFETs may be able to achieve a sub-thermal SS in a wide current range and, at the same time, very competitive on currents [1], as demonstrated by a recently fabricated vertical InAs/GaAsSb/GaSb nanowire n-type TFETs [10]. The aim of this work is to benchmark a complementary III-V TFET technology platform against the mainstream FinFET reference, by considering basic building blocks of digital and analog applications. To this purpose, we selected a complementary III-V TFET technology platform designed and optimized using full quantum simulations in [11], where n- and p-type TFET pairs are realized in the same InAs/AlGaSb material system. The use of such devices allowed us to remove the excessively optimistic assumption of perfectly symmetric n- and p-type TFETs, very frequently embraced in previous simulation studies (e.g. in [2, 7]). We present circuit-level simulations performed on current mirrors and inverter-based logic blocks, which are identified as basic topologies representative of the analog and digital design realms, respectively. Similar benchmarking results for the same technology platforms have been obtained by focusing the comparison on more complicated circuit blocks [3], [5] and [6]

Simulation study of Fermi level depinning in metal-MoS2 contacts

We used Density Functional Theory (DFT) to study the Fermi level pinning and Schottky barrier height in metal-MoS2 contacts. We showed that the Fermi level de-pinning could be attained by controlling the distance between the metal and MoS2. In particular, with proper buffer layers and the use of back-gated structures, the Schottky barrier height can be practically zeroed in some metal-MoS2 stacks, which is important to attain Ohmic contacts

Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies

The technological exploitation of ferroelectricity in CMOS electron devices offers new design opportunities, but also significant challenges from an integration, optimization and modelling perspective. We here revisit the working principle and the modelling of some novel ferroelectric based devices, with an emphasis on energy efficiency and on applications to new computational paradigms

Electromechanical Piezoresistive Sensing in Suspended Graphene Membranes

Monolayer graphene exhibits exceptional electronic and mechanical properties, making it a very promising material for nanoelectromechanical (NEMS) devices. Here, we conclusively demonstrate the piezoresistive effect in graphene in a nano-electromechanical membrane configuration that provides direct electrical readout of pressure to strain transduction. This makes it highly relevant for an important class of nano-electromechanical system (NEMS) transducers. This demonstration is consistent with our simulations and previously reported gauge factors and simulation values. The membrane in our experiment acts as a strain gauge independent of crystallographic orientation and allows for aggressive size scalability. When compared with conventional pressure sensors, the sensors have orders of magnitude higher sensitivity per unit area.Comment: 20 pages, 3 figure

Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits

In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-Transistor (TFET) virtual technology platform is benchmarked against the projection to the CMOS FinFET 10-nm node, by means of device and basic circuit simulations. The comparison is performed in the ultralow voltage regime (below 500 mV), where the proposed III-V TFETs feature ON-current levels comparable to scaled FinFETs, for the same low-operating-power OFF-current. Due to the asymmetrical n-and p-Type I-V exts , trends of noise margins and performances are investigated for different Wp/Wn ratios. Implications of the device threshold voltage variability, which turned out to be dramatic for steep slope TFETs, are also addressed